september 2013 dsc-3622/10 1 ? 2013 integrated device technology, inc. features 512k x 8 advanced high-speed cmos static ram jedec center power / gnd pinout for reduced noise equal access and cycle times ? commercial and industrial: 10/12/15ns single 3.3v power supply one chip select plus one output enable pin bidirectional data inputs and outputs directly ttl-compatible low power consumption via chip deselect available in 36-pin, 400 mil plastic soj package and 44-pin, 400 mil tsop. functional block diagram description the idt71v424 is a 4,194,304-bit high-speed static ram organized as 512k x 8. it is fabricated using high-perfomance, high-reliability cmos technology. this state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for high-speed memory needs. the idt71v424 has an output enable pin which operates as fast as 5ns, with address access times as fast as 10ns. all bidirectional inputs and outputs of the idt71v424 are ttl-compatible and operation is from a single 3.3v supply. fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. the idt71v424 is packaged in a 36-pin, 400 mil plastic soj and 44- pin, 400 mil tsop. address decoder 4,194,304-bit memory array i/o control ? ? ? a 0 a 18 8 8 i/o 0 -i/o 7 8 control logic we oe cs 3622 drw 01 ? ? ? 3.3v cmos static ram 4 meg (512k x 8-bit) idt71v424s idt71v424l
6.42 2 idt71v424s, idt71v424l, 3.3v cmos static ram 4 meg (512k x 8-bit) commercial and industrial temperature ranges 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a5 nc nc a9 a8 a7 we i/03 i/02 v ss v dd i/01 i/00 cs a2 a1 a0 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 nc nc a15 oe i/07 i/06 v ss v dd i/05 i/04 a14 a13 a11 a10 nc nc nc nc a12 so44-2 3622 drw 11 nc nc a3 a4 a6 a16 a17 a18 a0 a1 a2 a3 cs i/o 0 v dd v ss i/o 2 we a4 a5 a6 a7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc a18 a17 a16 oe i/o 7 i/o 6 v ss v dd i/o 5 a14 a13 a12 a11 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 so36-1 17 18 19 20 i/o 1 i/o 3 i/o 4 nc a8 a9 a10 a15 3622 drw 02 soj top view pin configuration truth table (1,2) capacitance (t a = +25c, f = 1.0mhz, soj package) pin configuration tsop top view a 0 ? a 18 address inputs input cs chip select input we write enable input oe output enable input i/o 0 - i/o 7 data input/output i/o v dd 3.3v power power v ss ground gnd 3622 tbl 02 pin description symbol parameter (1) conditions max. unit c in input capacitance v in = 3dv 7 pf c i/ o i/o capacitance v out = 3dv 8 pf 3622 tbl 03 note: 1. this parameter is guaranteed by device characterization, but not production tested. cs oe we i/o function llhdata out read data lx ldata in write data l h h high-z output disabled h x x high-z deselected - standby (i sb ) v hc (3) x x high-z deselected - standby (i sb1 ) 3622 tbl 01 notes: 1. h = v ih , l = v il , x = don't care. 2. v lc = 0.2v, v hc = v dd -0.2v. 3. other inputs v hc or v lc .
6.42 3 idt71v424s, idt71v424l, 3.3v cmos static ram 4 meg (512k x 8-bit) commercial and industrial temperature ranges absolute maximum ratings (1) recommended operating temperature and supply voltage recommended dc operating conditions dc electrical characteristics (v dd = min. to max., commercial and industrial temperature ranges) dc electrical characteristics (1, 2, 3) (v dd = min. to max., v lc = 0.2v, v hc = v dd ? 0.2v) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. notes: 1. v ih (max.) = v dd +2v for pulse width less than 5ns, once per cycle. 2. v il (min.) = ?2v for pulse width less than 5ns, once per cycle. notes: 1. all values are maximum guaranteed values. 2. all inputs switch between 0.2v (low) and v dd - 0.2v (high). 3. power specifications are preliminary. 4. f max = 1/t rc (all address inputs are cycling at f max ); f = 0 means no address input lines are changing. symbol rating value unit v dd supply voltage relative to v ss -0.5 to +4.6 v v in , v out terminal voltage relative to v ss -0.5 to v dd +0.5 v t bias temperature under bias -55 to +125 o c t stg storage temperature -55 to +125 o c p t power dissipation 1 w i out dc output current 50 ma 3622 tbl 04 symbol parameter min. typ. max. unit v dd supply voltage 3.0 3.3 3.6 v v ss ground 0 0 0 v v ih input high voltage 2.0 ____ v dd +0.3 (1) v v il input low voltage -0.3 (2 ) ____ 0.8 v 3622 tbl 06 grade temperature v ss v dd comm ercial 0c to +70c 0v see below industrial ?40c to +85c 0v see below 3622 tbl 05 symbol parameter test condition idt71v424 min. max. unit |i li | input leakage current v dd = max., v in = v ss to v dd ___ 5a |i lo | output leakage current v dd = max., cs = v ih , v out = v ss to v dd ___ 5a v ol output low voltage i ol = 8ma, v dd = min. ___ 0.4 v v oh output high voltage i oh = -4ma, v dd = min. 2.4 ___ v 3622 tbl 07 symbol parameter 71v424s/l 10 71v424s/l 12 71v424s/l 15 unit com'l. ind. com'l. ind. com'l. ind. i cc dynamic operating current cs < v lc , outputs open, v dd = max., f = f max (4) s 180 180 170 170 160 160 ma l 165 165 155 155 145 145 ma i sb dynamic standby power supply current cs > v hc , outputs open, v dd = max., f = f max (4) s606055 555050ma l555550 504545ma i sb1 full standby power supply current (static) cs > v hc , outputs open, v dd = max., f = 0 (4) s202020 202020ma l101010 101010ma 3622 tbl 08
6.42 4 idt71v424s, idt71v424l, 3.3v cmos static ram 4 meg (512k x 8-bit) commercial and industrial temperature ranges ac test loads ac test conditions figure 1. ac test load figure 2. ac test load (for t clz , t olz , t chz , t ohz , t ow, and t whz ) figure 3. output capacitive derating *including jig and scope capacitance. 3622 drw 04 320 350 5pf* data out 3.3v 1 2 3 4 5 6 7 20 40 60 80 100 120 140 160 180 200 t aa, t acs (typical, ns) capacitance (pf) 8 3622 drw 05 ? ? ? ? ? ? ? +1.5v 50 i/o z 0 =50 3622 drw 03 30pf input pulse levels input rise/fall times input timing reference levels output reference levels ac test load gnd to 3.0v 1.5ns 1.5v 1.5v see figure 1, 2 and 3 3622 tbl 09
6.42 5 idt71v424s, idt71v424l, 3.3v cmos static ram 4 meg (512k x 8-bit) commercial and industrial temperature ranges 71v424s/l10 71v424s/l12 71v424s/l15 symbol parameter min.max.min.max.min.max.unit read cycle t rc read cycle time 10 ____ 12 ____ 15 ____ ns t aa address access time ____ 10 ____ 12 ____ 15 ns t acs chip select access time ____ 10 ____ 12 ____ 15 ns t clz (1) chip select to output in low-z 4 ____ 4 ____ 4 ____ ns t chz (1) chip deselect to output in high-z ____ 5 ____ 6 ____ 7ns t oe output enable to output valid ____ 5 ____ 6 ____ 7ns t olz (1) output enable to output in low-z 0 ____ 0 ____ 0 ____ ns t ohz (1) output disable to output in high-z ____ 5 ____ 6 ____ 7ns t oh output hold from address change 4 ____ 4 ____ 4 ____ ns t pu (1) chip select to power up time 0 ____ 0 ____ 0 ____ ns t pd (1) chip deselect to power down time ____ 10 ____ 12 ____ 15 ns write cycle t wc write cycle time 10 ____ 12 ____ 15 ____ ns t aw address valid to end of write 8 ____ 8 ____ 10 ____ ns t cw chip select to end of write 8 ____ 8 ____ 10 ____ ns t as address set-up time 0 ____ 0 ____ 0 ____ ns t wp write pulse width 8 ____ 8 ____ 10 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ ns t dw data valid to end of write 6 ____ 6 ____ 7 ____ ns t dh data hold time 0 ____ 0 ____ 0 ____ ns t ow (1) output active from end of write 3 ____ 3 ____ 3 ____ ns t whz (1) write enable to output in high-z ____ 6 ____ 7 ____ 7ns 3622 tbl 10 note: 1. this parameter guaranteed with the ac load (figure 2) by device characterization, but is not production tested. ac electrical characteristics (v cc = 3.3v 10%, commercial and industrial temperature ranges)
6.42 6 idt71v424s, idt71v424l, 3.3v cmos static ram 4 meg (512k x 8-bit) commercial and industrial temperature ranges timing waveform of read cycle no. 2 (1, 2, 4) notes: 1. we is high for read cycle. 2. device is continuously selected, cs is low. 3. address must be valid prior to or coincident with the later of cs transition low; otherwise t aa is the limiting parameter. 4. oe is low. 5. transition is measured 200mv from steady state. timing waveform of read cycle no. 1 (1) address 3622 drw 06 oe cs data out (5) (5) (5) (5) data out valid high impedance t aa t rc t oe t acs t olz t chz t clz (3) t ohz v cc supply current t pu t pd i cc i sb data out address 3622 drw 07 t rc t aa t oh t oh data out valid previous data out valid
6.42 7 idt71v424s, idt71v424l, 3.3v cmos static ram 4 meg (512k x 8-bit) commercial and industrial temperature ranges timing waveform of write cycle no. 1 ( we controlled timing) (1, 2, 4) timing waveform of write cycle no. 2 ( cs controlled timing) (1, 4) notes: 1. a write occurs during the overlap of a low cs and a low we . 2. oe is continuously high. during a we controlled write cycle with oe low, t wp must be greater than or equal to t whz + t dw to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe is high during a we controlled write cycle, this requirement does not apply and the minimum write pulse is the specified t wp . 3. during this period, i/o pins are in the output state, and input signals must not be applied. 4. if the cs low transition occurs simultaneously with or after the we low transition, the outputs remain in a high impedance state. cs must be active during the t cw write period. 5. transition is measured 200mv from steady state. address cs we data out data in 3622 drw 08 (5) (2) (5) (5) data in valid high impedance t wc t aw t as t whz t wp t chz t ow t dw t dh t wr (3) (3) cs address data in 3622 drw 09 t aw t wc t cw t as t wr t dw t dh data in valid we
6.42 8 idt71v424s, idt71v424l, 3.3v cmos static ram 4 meg (512k x 8-bit) commercial and industrial temperature ranges ordering information x power xx speed xxx package x process/ temperature range blank i commercial (0c to +70c) industrial (?40c to +85c) y ph 36-pin 400 mil soj (so36-1) 44-pin tsop type ii (so44-2) 10 12 15 71v424 device type speed in nanoseconds 3622 drw 10 s l standard power low power x g green blank 8 tube or tray tape and reel x
6.42 9 idt71v424s, idt71v424l, 3.3v cmos static ram 4 meg (512k x 8-bit) commercial and industrial temperature ranges datasheet document history 8/13/99 updated to new format pg. 2 removed so44-1 from tsop pinout pg. 7 revised footnotes on write cycle no. 1 diagram removed footnote for t wr on write cycle no. 2 diagram pg. 9 added datasheet document history 8/31/99 pg. 1?9 added industrial temperature range offerings 11/22/02 pg. 8 added die revision option to ordering information 07/31/03 pg. 8 updated note, l10 speed grade commercial temperature only and updated die stepping from yf to y. 07/28/04 pg. 3 increased isb for all "l" and s15 speeds by 10ma and increased for s12 speed by 5ma (refer to pcn# sr-0402-02). pg. 8 added "restricted hazardous substance device" to the ordering information. 09/20/08 pg. 1, 8 added y and v step part numbers to front page and ordering information. updated the ordering information by removing the ?idt? notation. 05/12/09 pg. 3,5,8 add industrial grade for 10ns low power. 06/11/09 pg.1,8 removed vs, vl from datasheet and ordering information. 09/26/13: pg.1-9 removed the /ys & /yl from the device name for the entire datasheet. pg.1 removed idt's reference to fabrication. pg.8 updated ordering information by adding t&r, updated restricted hazardous substance device wording to green and removed the die stepping revision, the?y? designator. the idt logo is a registered trademark of integrated device technology, inc. corporate headquarters for sales: 6024 silver creek valley road 800-345-7015 or san jose, ca 95138 408-284-8200 fax: 408-284-2775 www.idt.com for tech support: sramhelp@idt.com 408-284-4532
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